On Tue, Sep 04, 2007 at 04:52:33PM +0800, yshi wrote: > perfmon2 patch changed timer interrupt handler of malta board. > When kernel handles timer interrupt, interrupt handler will read 30 bit > of cause register. If this bit is zero, timer interrupt handler will > exit, won't really handle interrupt. Because Malta 4kec board's core > revision is CoreFPGA-3, this core's cause register doesn't implement 30 > bit, so kernel always read zero from this bit. This will cause kernel > hang in calibrate_delay. You seem to have defined cpu_has_mips_r2 as 1 in your cpu_features_override.h file. Classic cut'n'paste error I'd guess :-) Ralf
