[PATCH] malta4kec hang in calibrate_delay fix

[yshi <yang.shi@xxxxxxxxxxxxx>]

perfmon2 patch changed timer interrupt handler of malta board.
When kernel handles timer interrupt, interrupt handler will read 30 bit
of cause register. If this bit is zero, timer interrupt handler will
exit, won't really handle interrupt. Because Malta 4kec board's core
revision is CoreFPGA-3, this core's cause register doesn't implement 30
bit, so kernel always read zero from this bit. This will cause kernel
hang in calibrate_delay.

Signed-off-by: Yang Shi <yang.shi@xxxxxxxxxxxxx>
---
b/arch/mips/mips-boards/generic/time.c |   17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
---

--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -136,11 +136,13 @@ irqreturn_t mips_timer_interrupt(int irq
#else /* CONFIG_MIPS_MT_SMTC */
     int r2 = cpu_has_mips_r2;

-       if (handle_perf_irq(r2))
-               goto out;
+       if (mips_revision_corid != MIPS_REVISION_CORID_CORE_FPGA3) {
+               if (handle_perf_irq(r2))
+                       goto out;

-       if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
-               goto out;
+               if (r2 && ((read_c0_cause() & (1 << 30)) == 0))
+                       goto out;
+       }

     if (cpu == 0) {
             /*
@@ -294,7 +296,12 @@ void __init plat_timer_setup(struct irqa
     {
             if (cpu_has_vint)
                     set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
-               mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+
+               if (mips_revision_corid != MIPS_REVISION_CORID_CORE_FPGA3)
+                       mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + 
cp0_compare_irq;
+               else
+                       mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE +
+                                            CP0_LEGACY_COMPARE_IRQ;
     }

     /* we are using the cpu counter for timer interrupts */