On Tue, 24 Jul 2007 22:20:34 +0100, Thiemo Seufer <ths@xxxxxxxxxxxx> wrote: > >> +#define cpu_has_mips32r1 0 > >> +#define cpu_has_mips32r2 0 > >> +#define cpu_has_mips64r1 0 > >> +#define cpu_has_mips64r2 0 > > > > Hm, really? > > IIRC it is MIPS IV. (tx99 is MIPS64R1). It is MIPS III. --- Atsushi Nemoto
