Hi, > > does it return if you write 0xc to the address 0x20 in the I/O port space > > and then read back from that location? You should complain to the > > manufacturer -- they may be able to fix the problem in a later revision. > > Haha, here's an excerpt form CS5535 spec. update: > > 96. PIC does not support Polling mode > > [...] > > Implications: This mode is not normally used in x86 systems. > Resolution: None. Yes, of course: $ grep OCW3 arch/i386/kernel/*.c arch/i386/kernel/time.c: outb(0x0c, PIC_MASTER_OCW3); not at all, indeed! > > You can still dispatch interrupts manually by examining the IRR register, > > but having a way to ask the 8259A's prioritiser would be nice. Although > > given such a lethal erratum you report I would not count on the prioritiser > > to provide any useful flexibility... > > Why not? AMD just decided not to implement poll mode, that's all. If they have decided to skip such an "unimportant" bit of logic, they could have skipped more, only providing support for the basic FNM INT/INTA/EOI scheme -- the only one "architecturally" supported from the original IBM PC on. And indeed, a brief look at the datasheed reveals they claim to have removed the SFNM too (which IMO provides a more reasonable nesting resolution and should be the default for setups where nesting is used, such as the environment as set up at the bootstrap by the PC BIOS). Maciej
