On Sun, 17 Jun 2007 15:36:53 +0200, "Franck Bui-Huu" <vagabon.xyz@xxxxxxxxx> wrote: > b) Are there some weird MIPS CPUs out there which don't read/ack cp0 > hpt in the normal way ? PNX8550? Their count/compare interrupt altomatically clears the count register. Please refer this thread: http://www.linux-mips.org/archives/linux-mips/2006-12/msg00194.html I'm not sure this fits new clockevent codes or not. --- Atsushi Nemoto
