Ralf Baechle wrote:
For the general MIPS case (Alchemy may provide guarantees I don't know of)
a SYNC instruction is not sufficient to ensure that a write has actually
been reached by the device. It may just like on PCI take a read from the
same device again:
I just looked it up.
Section 2.4.5 of the Alchemy Au1550 datasheet says that a SYNC is
guaranteed to commit the write buffer to memory.
Whoever is looking at this should also pay attention to the CCA bits in
the TLB mapping the registers (Section 2.3.6 of the manual) or the fixed
regions (depending on the VA used) to make sure that merging and
gathering are turned off.
--
Andrew Dyer <adyer@xxxxxxxxxxxxxxxxx>
Sr. Engineer
RightHand Technologies, Inc.
6545 N. Olmsted Ave.
Chicago, IL 60631
(773) 774-7600 x111
