On Mon, Mar 12, 2007 at 06:35:04PM +0300, Sergei Shtylyov wrote: > >>It might be ignorance on my part, but aren't au_sync()'s needed here? > > >My ignorance too.. What's au_sync()? Something to writeback/invalidate the > >cache? > > It's "memory barrier" (SYNC instruction). For the general MIPS case (Alchemy may provide guarantees I don't know of) a SYNC instruction is not sufficient to ensure that a write has actually been reached by the device. It may just like on PCI take a read from the same device again: au1000->ac97_ioport->config = AC97C_SG | AC97C_SYNC; au1000->ac97_ioport->config; udelay(100); au1000->ac97_ioport->config = 0x0; to ensure that all preceding write have actually made it. That also means that any use of the SYNC instruction may well be just an attempt to paper over a bug. Ralf
