Hello, I wrote:
+ +static void pnx8550_timer_ack(void) +{ + write_c0_compare(cycles_per_jiffy); +} + +static cycle_t pnx8550_hpt_read(void) +{ + /* FIXME: we should use timer2 or timer3 as freerun counter */ + return read_c0_count(); +}
I'd suggest read_c0_count2() here, possibly adding an interrupt handler for it since it will interrupt upon hitting compare2 reg. value (but we could probably just mask the IRQ off), and enabling the timer 2, of course (the current code disables it)...
No, we'll have to handle IRQ it once the timer is enabled -- there seems to be no provision to mask it off other than disabling the timer.
WBR, Sergei
