On Tue, 19 Dec 2006 00:17:24 -0800 (PST), Daniel Laird <danieljlaird@xxxxxxxxxxx> wrote: > On the PNX8550 it does not use the CP0 timer but use a different timer (the > Custom MIPS core has 3 extra timers) Do you know what this ifndef line mean? #ifndef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */ /* Ack this timer interrupt and set the next one. */ expirelo += cycles_per_jiffy; #endif If it means "On PNX8550, writing to COMPARE register resets COUNTER to zero", new time.c might be broken for PNX8550. Could you try this patch? diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index 11aab6d..4eb0741 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -119,7 +119,11 @@ static cycle_t c0_hpt_read(void) /* For use both as a high precision timer and an interrupt source. */ static void __init c0_hpt_timer_init(void) { +#ifdef CONFIG_SOC_PNX8550 /* pnx8550 resets to zero */ + expirelo = cycles_per_jiffy; +#else expirelo = read_c0_count() + cycles_per_jiffy; +#endif write_c0_compare(expirelo); }