On Wed, 24 May 2006, Ralf Baechle wrote: > > We have got PRId to filter out these. Though rev. 2 of the architecture > > limits conditions when to raise the exception so it may eventually be a > > non-issue. > > Doesn't really help, the exception is asynchronous by definition, so the > CPU can be far away by the time it's struck be the lightning bolt. > Machine check is just a _bad_ place to be. It does help -- while it is asynchronous indeed, TLB writes are far rarer than reads and happen in well defined places and a machine check will happen within limited time after such a write attempt, at the very worst. With the 4Kc the machine check looks synchronous. Maciej
