On Wed, May 24, 2006 at 04:11:12PM +0100, Maciej W. Rozycki wrote: > > Depends on when exactly a CPU will raise the machine check. On some cores > > the information in registers is totally useless if not even missloading. > > We have got PRId to filter out these. Though rev. 2 of the architecture > limits conditions when to raise the exception so it may eventually be a > non-issue. Doesn't really help, the exception is asynchronous by definition, so the CPU can be far away by the time it's struck be the lightning bolt. Machine check is just a _bad_ place to be. > > But generally a good idea, patch below. > > Except Index would be a bit more useful than HI. ;-) Index may not matter at all in case of a TLBWR. But yes, will include index in the patch. Ralf
