>>>>> On Tue, 14 Feb 2006 16:07:29 +0900, Yoichi Yuasa <yoichi_yuasa@xxxxxxxxxxxxxx> said: yuasa> I added the patch and tested it. It has same problem. Thank you. I realize the reason just now. VR41XX's PTE format is a bit different from others. I should use mk_pte() to wrap these difference. Could you try this patch? 64BIT_PHYS_ADDR + MIPS32_R1 part are not tested ;-) --- linux-mips/arch/mips/mm/init.c 2006-02-14 15:30:58.000000000 +0900 +++ linux/arch/mips/mm/init.c 2006-02-14 16:29:51.000000000 +0900 @@ -95,6 +95,7 @@ static inline void *kmap_coherent(struct unsigned long asid; unsigned int vpflags; unsigned int wired; + pte_t pte; if (!cpu_has_dc_aliases) return page_address(page); @@ -111,8 +112,13 @@ static inline void *kmap_coherent(struct wired = read_c0_wired(); write_c0_wired(wired + 1); write_c0_index(wired); - write_c0_entryhi(vaddr & ~0x1fffUL); - entrylo = (page_to_pfn(page) << 6) | (pgprot_val(PAGE_KERNEL) >> 6); + write_c0_entryhi(vaddr & (PAGE_MASK << 1)); + pte = mk_pte(page, PAGE_KERNEL); +#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1) + entrylo = pte.pte_high; +#else + entrylo = pte_val(pte) >> 6; +#endif write_c0_entrylo0(entrylo); write_c0_entrylo1(entrylo); mtc0_tlbw_hazard();
