Hello,
r4k_dma_cache_wback_inv and r4k_dma_cache_inv always had the same function
body. With some invocations (on some machine at least ;) this does not only
affect performance, but also is corrupting (dma-)memory, so it had to be
adjusted in the IP28-patches from the beginning. I had some correspondence
with Ralf about it some months ago. He hesitated to take over this changes
because of the reasons mentioned below. (so btw. IP28 got its own
r10k_dma_cache_inv :)
kind regards
pf
On Mon, 19 Sep 2005, Thiemo Seufer wrote:
> Date: Mon, 19 Sep 2005 17:40:56 +0200
> From: Thiemo Seufer <ths@xxxxxxxxxxxx>
> Reply-To: linux-mips-bounce@xxxxxxxxxxxxxx
> To: linux-mips@xxxxxxxxxxxxxx
> Subject: Performance bug in c-r4k.c cache handling code
>
> Hello All,
>
> I found an performance bug in c-r4k.c:r4k_dma_cache_inv, where a
> Hit_Writeback_Inv instead of Hit_Invalidate is done. Ralf mentioned
> this is probably due to broken Hit_Invalidate cache ops on some
> CPUs, does anybody have more information about this? The appended
> patch works apparently fine on R4400, R4600v2.0, R5000.
>
>
> Thiemo
>
>
> Index: arch/mips/mm/c-r4k.c
> ===================================================================
> RCS file: /home/cvs/linux/arch/mips/mm/c-r4k.c,v
> retrieving revision 1.119
> diff -u -p -r1.119 c-r4k.c
> --- arch/mips/mm/c-r4k.c 9 Sep 2005 20:26:54 -0000 1.119
> +++ arch/mips/mm/c-r4k.c 19 Sep 2005 15:33:35 -0000
> @@ -685,7 +685,7 @@ static void r4k_dma_cache_inv(unsigned l
> a = addr & ~(sc_lsize - 1);
> end = (addr + size - 1) & ~(sc_lsize - 1);
> while (1) {
> - flush_scache_line(a); /* Hit_Writeback_Inv_SD */
> + invalidate_scache_line(a); /* Hit_Invalidate_SD */
> if (a == end)
> break;
> a += sc_lsize;
> @@ -702,7 +702,7 @@ static void r4k_dma_cache_inv(unsigned l
> a = addr & ~(dc_lsize - 1);
> end = (addr + size - 1) & ~(dc_lsize - 1);
> while (1) {
> - flush_dcache_line(a); /* Hit_Writeback_Inv_D */
> + invalidate_dcache_line(a); /* Hit_Invalidate_D */
> if (a == end)
> break;
> a += dc_lsize;
>
>
