On Mon, 07 Feb 2005 19:24:50 +0900 (JST) Atsushi Nemoto <anemo@xxxxxxxxxxxxx> wrote: > >>>>> On Fri, 4 Feb 2005 15:58:03 +0100, Ralf Baechle <ralf@xxxxxxxxxxxxxx> said: > ralf> That's not a new feature in the MIPS world; the R10000 family > ralf> introduced that first and Linux knows how to make use of it. So > ralf> now I just need to teach c-r4k.c to check the AR bit on the 24K. > > 20KC Users Manual says it has physically indexed data cache. > > --- linux-mips.org/arch/mips/mm/c-r4k.c 2005-02-07 19:06:54.598390493 +0900 > +++ linux-mips/arch/mips/mm/c-r4k.c 2005-02-07 19:10:38.779771207 +0900 > @@ -1016,6 +1016,8 @@ > case CPU_R10000: > case CPU_R12000: > break; > + case CPU_20KC: /* physically indexed */ > + break; > case CPU_24K: > if (!(read_c0_config7() & (1 << 16))) > default: > > For other MIPS64 core, 5Kc has virtually indexed cache. How about 25KF? 25Kf also has virtually indexed cache. Yoichi
