Atsushi Nemoto wrote:
This code is wrong (should be "c->dcache.waysize > PAGE_SIZE") and unnecessary (done correctly in probe_pcache).
diff -u -r1.96 c-r4k.c --- arch/mips/mm/c-r4k.c 7 Dec 2004 02:33:02 -0000 1.96 +++ arch/mips/mm/c-r4k.c 4 Feb 2005 14:01:35 -0000 @@ -1213,9 +1213,6 @@ probe_pcache(); setup_scache();
- if (c->dcache.sets * c->dcache.ways > PAGE_SIZE) - c->dcache.flags |= MIPS_CACHE_ALIASES; - r4k_blast_dcache_page_setup(); r4k_blast_dcache_page_indexed_setup(); r4k_blast_dcache_setup();
Also, some MIPS32/MIPS64 chip have physically indexed data cache so do
no suffer from aliasing. CPU_20KC is one of them. Others?
The MIPS 24K family's caches are not physically indexed, but they do have optional h/w assist to prevent aliases in certain cache configurations. This optional feature is indicated by the read-only AR (alias removed) flag being set - that's bit 16 in the CP0 Config7 register.
Nigel
