Hi,
Is there any specific reason why the cache invalidation routine is executed with interrupts disabled?
Example:
static void
mips32_dma_cache_inv_pc(unsigned long addr, unsigned long size)
{
unsigned long end, a;
unsigned int flags;
if (size >= dcache_size) {
flush_cache_all();
} else {
__save_and_cli(flags);
a = addr & ~(dc_lsize - 1);
end = (addr + size) & ~(dc_lsize - 1);
while (1) {
flush_dcache_line(a); /* Hit_Writeback_Inv_D */
if (a == end) break;
a += dc_lsize;
}
__restore_flags(flags);
}
bc_inv(addr, size);
}
Thanks.
- Pankaj
