On Tue, Nov 18, 2003 at 06:57:41AM -0000, ashish anand wrote: > 1.If i have a compulsion to use egde triggering peripheral on MIPS CP0, > would it be useful if i can increase the assertion duration of edge > interupts (this I can do) ..I mean to say probablity of loosing edge > interrupts will decrasse. That would help but still not be a safe mechanism. Not only the processor may be missing the edge - Linux may also disable interrupts for quite a long time. You'd have to use a hard realtime variant of Linux or you will loose interrupts ... > 2.does CP0 interrupt logic samples interrupts after each instruction or > at some multiplication(..or division.?) of system clock. This is a very processor specific detail. R4000 for example will sample interrupts on pipe stage 3; something along that lines is probably done in most in-order processors. Ralf
