On Mon, Nov 17, 2003 at 11:40:11AM -0000, ashish anand wrote: > I have a generic question regarding interrupt controler functionality > integrated in CP0 on mips architecture. > I don't see any interface to configure the edge/level triggering settings. MIPS only supports level triggered interrupts in coprocessor 0. > though in our BSP we take care of handling spurious interrupts , but is > this designed to be like that..? There is no handling needed. If the processor takes an interrupt but none of the interrupt bits in c0_status is set, just return. That's a legal condition. > I mean to ask , suppose I want to add a edge triggering peripheral. > to the extent of my understanding this will certainly generate the > spurious interrupts when coupled with a level triggering configuration > in CP0 (by default..?). You can directly sample the level of the edge irq in the interrupt bits in the cause register. But that seems a fragile approach. > if i am handling through CP0_CAUSE or any other register inspection > that can work but I am loosing so many valid interupts which would have > been really valid with edge trigger pin of interrupt controller . > further this type of handling is valid for actual spurious interrupts > not for those who are certain to be fired because of edge/level mismatching. If you really need to use an edge triggered interrupt on a MIPS then you probably want to use some circuit interrupt controller that converts the edge to a level triggered interrupt. Ralf
