Ashish, > would a spurious interrupt ( edge vs. level trigger mismatching) > cause CP0_CAUSE to show any pending interupts.? CP0_CAUSE reflects the real-time inputs to the CPU, not the state of those inputs at the time the interrupt was detected, nor is it sensitive to the "mask" bits in the status register. So it's perfectly possible to find no active bits in CP0_CAUSE which account for your interrupt. But it does all depend how your interrupt controller works... -- Dominic Sweetman MIPS Technologies
