On Wed, Oct 15, 2003 at 04:23:06PM +0200, Maciej W. Rozycki wrote: > > Still want more? A 3 level tree would then cover 128TB of virtual > > address space already exceedin the hardware limits of all processors but > > the R8000. > > Well, the MIPS64 ISA spec allows up to 8EB of user memory to be supported > by an implementation, IIRC; probably nothing supports that much yet, > though. ;-) BTW, is an R8000 spec available online anywhere? There used to be a few papers published by SGI online and various other bits of information I found through google. (I happen to have a paper copy of the R8000 manual but since the responsible people still haven't informed me if I can legally use it, this book is closed and will stay closed until this happens - if ever ... Pitty, I still receive mails from various R8000 users ...) > > 64k pagesize stretches the limits even further. Here a two level > > pagetable tree would cover 4TB, 3-level could cover 32PB exceeding > > the capacity of every MIPS processor ever made - and probably sufficient > > for the coming decade :-) > > Further increasing of the page size should result in better performance > due to fewer TLB misses and reduce the memory footprint of page tables, > but the drawback is more memory is wasted for maps. Whether the end > result is a gain or a loss depends on the actual application of a system, > so I guess we should either leave the size configurable (with a sane > default for those who might have troubles judging what would suit them > best) or only decide on a given size after lots of benchmarking. Unless somebody yells I almost feel like ditching 3-level pagetable support; 2-levels with a decent pagesize should suffice for a few years to come ... Ralf
