On Tue, 14 Oct 2003, Ralf Baechle wrote: > Still want more? A 3 level tree would then cover 128TB of virtual > address space already exceedin the hardware limits of all processors but > the R8000. Well, the MIPS64 ISA spec allows up to 8EB of user memory to be supported by an implementation, IIRC; probably nothing supports that much yet, though. ;-) BTW, is an R8000 spec available online anywhere? > 64k pagesize stretches the limits even further. Here a two level > pagetable tree would cover 4TB, 3-level could cover 32PB exceeding > the capacity of every MIPS processor ever made - and probably sufficient > for the coming decade :-) Further increasing of the page size should result in better performance due to fewer TLB misses and reduce the memory footprint of page tables, but the drawback is more memory is wasted for maps. Whether the end result is a gain or a loss depends on the actual application of a system, so I guess we should either leave the size configurable (with a sane default for those who might have troubles judging what would suit them best) or only decide on a given size after lots of benchmarking. Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
