> If this is just to ensure the I Cache coherency for modified code > then the following should be sufficient: > > cache Hit_Writeback_D, offset(base_register) > cache Hit_Invalidate_I, offset(base_register) > > The ordering does matter however since the Hit_Invalidate_I makes > sure the write buffer is flushed. I'm probably jumping into the middle of something, sorry... The MIPS32/MIPS64 release 2 architecture includes a useful instruction SYNCI which does the whole job (repeat on each affected cache line) and is legal in user mode; this will take a while to spread but I'd recommend it as a model worth following. So I hope that kernels will provide one function for "I've just written instructions and now I want to execute them", and not export the separate writeback-D/invalidate-I interface. -- Dominic Sweetman MIPS Technologies dom@mips.com
