Hi, If this is just to ensure the I Cache coherency for modified code then the following should be sufficient: cache Hit_Writeback_D, offset(base_register) cache Hit_Invalidate_I, offset(base_register) The ordering does matter however since the Hit_Invalidate_I makes sure the write buffer is flushed. Kind Regards, _______________________________ Adam Kiepul Sr. Applications Engineer PMC-Sierra, Microprocessor Division Mission Towers One 3975 Freedom Circle Santa Clara, CA 95054, USA Direct: 408 239 8124 Fax: 408 492 9462 -----Original Message----- From: Ralf Baechle [mailto:ralf@linux-mips.org] Sent: Thursday, July 31, 2003 4:47 AM To: Fuxin Zhang Cc: MAKE FUN PRANK CALLS Subject: Re: RM7k cache_flush_sigtramp On Thu, Jul 31, 2003 at 09:56:08AM +0800, Fuxin Zhang wrote: > Date: Thu, 31 Jul 2003 09:56:08 +0800 > From: Fuxin Zhang <fxzhang@ict.ac.cn> > To: MAKE FUN PRANK CALLS <linux-mips@linux-mips.org> ^^^^^^^^^^^^^^^^^^^^ Funny name for the list :-) > r4k_cache_flush_sigtrap seems not enough for RM7000 cpus because > there is a writebuffer between L1 dcache & L2 cache,so the written back > block may not be seen by icache. This small patch fixes crashes of my > Xserver on ev64240. It would seem a similar fix is also needed in other places then? Ralf
