[PATCH] waybit not set for MIPS32/MIPS64 caches

[Chris Dearman <chris@mips.com>]

Hi Ralf,
  The unified cache code (c-r4k.c) does not set the waybit for 
MIPS32/MIPS64 processors.  This patch needs to be applied to 
{mips,mips64}/mm/c-r4k.c in 2.4 and 2.5.

	Chris

--
Chris Dearman          The Fruit Farm, Ely Road    voice +44 1223 706206
MIPS Technologies (UK) Chittering, Cambs, CB5 9PH  fax   +44 1223 706250

Index: arch/mips/mm/c-r4k.c
===================================================================
RCS file: /home/cvs/linux/arch/mips/mm/c-r4k.c,v
retrieving revision 1.3.2.40
diff -u -r1.3.2.40 c-r4k.c
--- arch/mips/mm/c-r4k.c	14 Apr 2003 03:49:59 -0000	1.3.2.40
+++ arch/mips/mm/c-r4k.c	15 Apr 2003 12:47:58 -0000
@@ -738,6 +738,7 @@
 		icache_size = c->icache.sets *
 		              c->icache.ways *
 		              c->icache.linesz;
+		c->icache.waybit = ffs(icache_size/c->icache.ways) - 1;
 
 		/*
 		 * Now probe the MIPS32 / MIPS64 data cache.
@@ -754,6 +755,7 @@
 		dcache_size = c->dcache.sets *
 		              c->dcache.ways *
 		              c->dcache.linesz;
+		c->dcache.waybit = ffs(dcache_size/c->dcache.ways) - 1;
 		break;
 	}