On Fri, Apr 11, 2003 at 07:33:04AM +0100, Dominic Sweetman wrote: > > > I'm not sure what you mean by TLB translations required for hit > > > cacheops. If you mean the Index Writeback or Index Invalidate > > > functions, note that you can (and should) use a kseg0 address to > > > do this. > > Mike was proposing a kseg0 address translating to the right physical > address, and used with a hit-type cacheop. I believe Ralf (and Linux) > are just assuming that's no good because it doesn't work if you have > cacheable memory above 512Mbytes physical address. > > I wonder whether anything really bad would happen if you temporarily > changed the (machine) ASID to that of the address space you wanted to > invalidate? There are non-trivial race conditions related to the IPI mechanism used on multi-processors when attempting this. The easy fix would be temporarily disabling interrupts - but of course that's undesireable as well. Ralf
