On Thu, Apr 10, 2003 at 12:37:47PM -0700, Mike Uhler wrote: > > The question came up between Jun and me when revising the way of handling > > multi-way caches. There is the MIPS32 / MIPS64 way of selecting the > > cache way - but that scheme was originally already introduced by the > > R4600. The second somewhat less common scheme is using the lowest bits > > of the address. That was originally introduced with the R10000 but a > > few other processors such as the R5432 and the TX49 series are using it > > as well. Unfortunately there has been way to much creativity (usually > > a positive property but ...) among designers so this posting is an > > attempt to achieve completeness. > > Exactly why we made it a standard in MIPS32 and MIPS64. Yep, of the existing variations that was certainly the nicest. Only a single function had to be taught about multi-way caches and that only because it's a bit hard to flush caches for another process due to the TLB translation required for the hit cacheops. Alternative schemes need more support by the code. Ralf
