On Thu, Apr 10, 2003 at 11:50:53AM -0700, Mike Uhler wrote: > > > > If a cache is multi-way set associative cache, one must > > select the way for indexed cache operations. > > > > The most common way selection is to use MSBs in the addressing > > range of the whole cache size. In other word, a two-way > > cache of size d would use bit (log(d)-1) to select the way. > > > > Some other CPUs often the LSB(s) in the address to select > > ways. Examples include R5432, R5500, TX49, TX39. Does > > anybody know other such CPUs? > > > > And I think I have seen a third kind way selection, but I > > can't remember which CPU it is. Does anybody know any > > other way selection schemes? > > > > Thanks. > > > > Jun > > > > I can't comment on anything but MIPS32 and MIPS64 CPUs, but the > MIPS32 and MIPS64 standard is to use the bits above the index field > to specify the way. Yes. This is same as the "most common case" as I said above. Maybe this is a better way to phrase it. :) Jun
