If a cache is multi-way set associative cache, one must select the way for indexed cache operations. The most common way selection is to use MSBs in the addressing range of the whole cache size. In other word, a two-way cache of size d would use bit (log(d)-1) to select the way. Some other CPUs often the LSB(s) in the address to select ways. Examples include R5432, R5500, TX49, TX39. Does anybody know other such CPUs? And I think I have seen a third kind way selection, but I can't remember which CPU it is. Does anybody know any other way selection schemes? Thanks. Jun
