Maciej W. Rozycki (macro@ds2.pg.gda.pl) writes: > Hmm, that's even more interesting -- how can instruction fetches be > distinguished from data reads externally??? The length of the burst is encoded in the bus command sent out by the R4000 at the beginning of a read or write cycle. For the system to work, the memory controller has to be able to do the right thing for both of the lengths which might happen... It's very hard to see how a system could fail to work by making the I-cache line the same size as a D-cache line. > Then again, the memory controller shouldn't be able to observe > inter-cache data moves. This is true: for L2-equipped chips I assume you can't see the difference between I- and D-. -- Dominic MIPS Technologies UK.
