>>A small question.. >> >>1.my understanding of wired tlb entries mean set of address translations >>that i always want to be present throughout the system is on , >>irrespective of asid's/tlb flush , examplesake pci io/mem window ...is >>this right? >> >>2.can i acheive the same by using the global bit from entrylo0 and >>entrylo1. >> >>Best Regards, >>Ashish Anand A wired entry can EITHER be irrespective of ASID (if the G bit for the entry is set) OR can take the current ASID into account (if the G bit for the entry is clear) -- using wired TLB entries to map things like PCI io/mem window is an example of a translation that would be fixed regardless of the process and therefore you would want to set the G bit (which would make the ASID field "don't care") Neal.
