On Fri, Feb 21, 2003 at 01:11:58PM +0100, Maciej W. Rozycki wrote: > > > Does Cobalt have a processor that implements its pipeline differently or > > > interlocks on CP0 loads? If not, I'll apply the following fix. > > > > Mfc0 doesn't need a nops on any R4000 class CPU I know of. > > Well, my MIPS R4k manual is vague on this matter and my IDT software > manual for R3k, R4k, R5k is even explicit on the load delay slot of mfc0. > But a run-time test proves otherwise. > > I stand corrected then unless someone finds a counter-example. All I can say it's working fine like this since 1984 for R4000 class CPUs. Ralf
