Hello, Does Cobalt have a processor that implements its pipeline differently or interlocks on CP0 loads? If not, I'll apply the following fix. Maciej -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available + patch-mips-2.4.20-20030214-cobalt-int-0 diff -up --recursive --new-file linux-mips-2.4.20-20030214.macro/arch/mips/cobalt/int-handler.S linux-mips-2.4.20-20030214/arch/mips/cobalt/int-handler.S --- linux-mips-2.4.20-20030214.macro/arch/mips/cobalt/int-handler.S 2003-01-28 03:56:27.000000000 +0000 +++ linux-mips-2.4.20-20030214/arch/mips/cobalt/int-handler.S 2003-02-15 10:28:15.000000000 +0000 @@ -31,6 +31,7 @@ */ mfc0 s0,CP0_CAUSE # get raw irq status mfc0 a0,CP0_STATUS # get irq mask + nop and s0,s0,a0 # compute masked irq status andi a0,s0,CAUSEF_IP2 /* Check for Galileo timer */
