Hello,
Here's a new version as promised. It works for me. OK to apply?
Maciej
--
+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+--------------------------------------------------------------+
+ e-mail: macro@ds2.pg.gda.pl, PGP key available +
patch-mips-2.4.19-rc1-20020821-mips64-vec3_r4000-6
diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020821.macro/arch/mips64/kernel/r4k_genex.S linux-mips-2.4.19-rc1-20020821/arch/mips64/kernel/r4k_genex.S
--- linux-mips-2.4.19-rc1-20020821.macro/arch/mips64/kernel/r4k_genex.S 2002-07-15 02:57:48.000000000 +0000
+++ linux-mips-2.4.19-rc1-20020821/arch/mips64/kernel/r4k_genex.S 2002-08-27 19:43:24.000000000 +0000
@@ -5,6 +5,7 @@
*
* Copyright (C) 1994 - 1999 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics
+ * Copyright (C) 2002 Maciej W. Rozycki
*
* Low level exception handling
*/
@@ -31,25 +32,28 @@
BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
BUILD_HANDLER reserved reserved sti verbose /* others */
+
__INIT
/* General exception handler for CPUs with virtual coherency exception.
*
- * Be careful when changing this, it has to be at most 128 bytes to fit
- * into space reserved for the exception handler.
+ * Be careful when changing this, it has to be at most 256 (as a special
+ * exception) bytes to fit into space reserved for the exception handler.
*/
- NESTED(except_vec3_r4000, 0, sp)
+ .set push
.set noat
-#if defined(R5432_CP0_INTERRUPT_WAR)
- mfc0 k0, CP0_INDEX
-#endif
+NESTED(except_vec3_r4000, 0, sp)
mfc0 k1, CP0_CAUSE
- andi k1, k1, 0x7c
li k0, 31<<2
+ andi k1, k1, 0x7c
+ .set push
+ .set noreorder
+ .set nomacro
beq k1, k0, handle_vced
li k0, 14<<2
beq k1, k0, handle_vcei
dsll k1, k1, 1
+ .set pop
ld k0, exception_handlers(k1)
jr k0
@@ -60,51 +64,61 @@
* store will be re-executed.
*/
handle_vced:
- mfc0 k0, CP0_BADVADDR
+ dmfc0 k0, CP0_BADVADDR
li k1, -4 # Is this ...
and k0, k1 # ... really needed?
mtc0 zero, CP0_TAGLO
cache Index_Store_Tag_D,(k0)
cache Hit_Writeback_Inv_SD,(k0)
- lui k0, %hi(vced_count)
- lw k1, %lo(vced_count)(k0)
+ dla k0, vced_count
+ lw k1, (k0)
addiu k1, 1
- sw k1, %lo(vced_count)(k0)
+ sw k1, (k0)
eret
handle_vcei:
- mfc0 k0, CP0_BADVADDR
+ dmfc0 k0, CP0_BADVADDR
cache Hit_Writeback_Inv_SD,(k0) # also cleans pi
- lui k0, %hi(vcei_count)
- lw k1, %lo(vcei_count)(k0)
+ dla k0, vcei_count
+ lw k1, (k0)
addiu k1, 1
- sw k1, %lo(vcei_count)(k0)
+ sw k1, (k0)
eret
+END(except_vec3_r4000)
+ .set pop
- END(except_vec3_r4000)
- .set at
- /* General exception vector for all other CPUs. */
- NESTED(except_vec3_generic, 0, sp)
+/* General exception vector for all other CPUs.
+ *
+ * Be careful when changing this, it has to be at most 128 bytes
+ * to fit into space reserved for the exception handler.
+ */
+ .set push
.set noat
+NESTED(except_vec3_generic, 0, sp)
+#if defined(R5432_CP0_INTERRUPT_WAR)
+ mfc0 k0, CP0_INDEX
+#endif
mfc0 k1, CP0_CAUSE
andi k1, k1, 0x7c
dsll k1, k1, 1
ld k0, exception_handlers(k1)
jr k0
- nop
- END(except_vec3_generic)
- .set at
+END(except_vec3_generic)
+ .set pop
+
/*
- * Special interrupt vector for embedded MIPS. This is a dedicated interrupt
- * vector which reduces interrupt processing overhead. The jump instruction
- * will be inserted here at initialization time. This handler may only be 8
- * bytes in size!
+ * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
+ * This is a dedicated interrupt exception vector which reduces the
+ * interrupt processing overhead. The jump instruction will be replaced
+ * at the initialization time.
+ *
+ * Be careful when changing this, it has to be at most 128 bytes
+ * to fit into space reserved for the exception handler.
*/
NESTED(except_vec4, 0, sp)
1: j 1b /* Dummy, will be replaced */
- nop
- END(except_vec4)
+END(except_vec4)
__FINIT
diff -up --recursive --new-file linux-mips-2.4.19-rc1-20020821.macro/arch/mips64/kernel/traps.c linux-mips-2.4.19-rc1-20020821/arch/mips64/kernel/traps.c
--- linux-mips-2.4.19-rc1-20020821.macro/arch/mips64/kernel/traps.c 2002-08-06 02:57:36.000000000 +0000
+++ linux-mips-2.4.19-rc1-20020821/arch/mips64/kernel/traps.c 2002-08-27 19:45:20.000000000 +0000
@@ -627,13 +627,15 @@ asmlinkage void do_watch(struct pt_regs
* We use the watch exception where available to detect stack
* overflows.
*/
- dump_tlb_all();
show_regs(regs);
+ dump_tlb_all();
panic("Caught WATCH exception - probably caused by stack overflow.");
}
asmlinkage void do_mcheck(struct pt_regs *regs)
{
+ extern void dump_tlb_all(void);
+
show_regs(regs);
dump_tlb_all();
/*
@@ -737,8 +739,11 @@ void __init trap_init(void)
per_cpu_trap_init();
/* Copy the generic exception handlers to their final destination. */
+ memcpy((void *)KSEG0, &except_vec0, 0x80);
+ /* Debug TLB refill handler. */
memcpy((void *)(KSEG0 + 0x100), &except_vec2_generic, 0x80);
memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic, 0x80);
+ memcpy((void *)(KSEG0 + 0x200), &except_vec4, 0x80);
/*
* Setup default vectors
@@ -753,23 +758,32 @@ void __init trap_init(void)
watch_init(mips_cpu.cputype);
/*
- * Some MIPS CPUs have a dedicated interrupt vector which reduces the
- * interrupt processing overhead. Use it where available.
- */
- memcpy((void *)(KSEG0 + 0x200), &except_vec4, 8);
-
- if (mips_cpu.options & MIPS_CPU_MCHECK)
- set_except_vector(24, handle_mcheck);
-
- /*
* The Data Bus Errors / Instruction Bus Errors are signaled
* by external hardware. Therefore these two exceptions
* may have board specific handlers.
*/
bus_error_init();
+ set_except_vector(4, handle_adel);
+ set_except_vector(5, handle_ades);
+
+ set_except_vector(6, handle_ibe);
+ set_except_vector(7, handle_dbe);
+
+ set_except_vector(8, handle_sys);
+ set_except_vector(9, handle_bp);
+ set_except_vector(10, handle_ri);
+ set_except_vector(11, handle_cpu);
+ set_except_vector(12, handle_ov);
+ set_except_vector(13, handle_tr);
+ set_except_vector(15, handle_fpe);
+
+ if (mips_cpu.options & MIPS_CPU_MCHECK)
+ set_except_vector(24, handle_mcheck);
+
/*
- * Handling the following exceptions depends mostly of the cpu type
+ * Handling of the following exceptions mostly depends
+ * on the CPU type.
*/
switch(mips_cpu.cputype) {
case CPU_SB1:
@@ -801,38 +815,25 @@ void __init trap_init(void)
case CPU_5KC:
case CPU_20KC:
case CPU_RM7000:
- /* Debug TLB refill handler. */
- memcpy((void *)KSEG0, &except_vec0, 0x80);
if ((mips_cpu.options & MIPS_CPU_4KEX)
&& (mips_cpu.options & MIPS_CPU_4KTLB)) {
memcpy((void *)KSEG0 + 0x080, &except_vec1_r4k, 0x80);
} else {
memcpy((void *)KSEG0 + 0x080, &except_vec1_r10k, 0x80);
}
+
if (mips_cpu.options & MIPS_CPU_VCE) {
+ /* VCE and DIVEC are mutually exclusive. */
+ if (mips_cpu.options & MIPS_CPU_DIVEC)
+ BUG();
memcpy((void *)(KSEG0 + 0x180), &except_vec3_r4000,
- 0x80);
- } else {
- memcpy((void *)(KSEG0 + 0x180), &except_vec3_generic,
- 0x80);
+ 0x100);
}
set_except_vector(1, __xtlb_mod);
set_except_vector(2, __xtlb_tlbl);
set_except_vector(3, __xtlb_tlbs);
- set_except_vector(4, handle_adel);
- set_except_vector(5, handle_ades);
-
- set_except_vector(6, handle_ibe);
- set_except_vector(7, handle_dbe);
- set_except_vector(8, handle_sys);
- set_except_vector(9, handle_bp);
- set_except_vector(10, handle_ri);
- set_except_vector(11, handle_cpu);
- set_except_vector(12, handle_ov);
- set_except_vector(13, handle_tr);
- set_except_vector(15, handle_fpe);
break;
case CPU_R8000:
