On Thu, 11 Jul 2002, Gleb O. Raiko wrote: > Have to check the cacheline at given address again. D-cache may have the > valid bit set for the cacheline at the same address. Address means > location in a cache, not memory. Check at address requires one extra > tick as opposed to checking the bit. Well, you issue an instruction word read from the cache. The answer is either a hit, providing a word at the data bus at the same time (so you can't get a hit from one cache and data from the other) or a miss with no valid data -- you have to stall in this case, waiting for a refill. Then when data from the main memory arrives, it is latched in the cache (it doesn't really matter, which one now -- if it's the wrong one, then another refill will happen next time the memory address is dereferenced) and provided to the CPU at the same time. > Please, note that CPU isn't a monolitic program, but rather a set of > functional blocks, so "proper implementation" may require additional > signals on wires and delays. Some kind of synchronization is needed as everywhere in the CPU, as it's mostly a synchronous circuit. As long as the state at clock edges is consistent, there is no problem with cache swapping. That's what I mean by a "proper implementation". -- + Maciej W. Rozycki, Technical University of Gdansk, Poland + +--------------------------------------------------------------+ + e-mail: macro@ds2.pg.gda.pl, PGP key available +
