On Tue, Jun 18, 2002 at 10:03:47AM -0700, William Jhun wrote:
> To: "linux-mips@oss.sgi.com"@ayrnetworks.com
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Your mail software is smoking funny stuff ;-)
> This is a re-hash of patches I sent out a while ago which do a more
> optimal cache-flushing for pci_map_*() and pci_dma_sync_*(). It
> basically does an invalidate for PCI_DMA_FROMDEVICE operations and a
> writeback for PCI_DMA_TODEVICE pci_map_* (or writeback/invalidate if
> PCI_DMA_BIDIRECTIONAL). This is similar to the ARM implementation.
>
> Additionally, I filled in the _dma_cache_wback calls in the
> arch/mips/c-*.c to call *_dma_cache_wback_inv* instead of calling
> panic(). Some architectures could probably do a real writeback instead
> of just wback_inv, but this will at least allow code that can use
> writeback-only if available.
>
> Note: I'm not familiar with a lot of these CPUs, but the change should
> be innocuous. Could someone validate/improve these?
Can you try to get rid of all these #ifdef CONFIG_NONCOHERENT_IO things?
We already had too many of them and you're adding even more ...
Basically if dma_cache_wback_inv, dma_cache_wback and dma_cache_inv are
just empty macros as they are if CONFIG_NONCOHERENT_IO is undefined
gcc should be able to optimize most of the #ifdef'd code away.
Please always cc patches you want to submit to me or I might miss them on
the list.
Ralf
