On Fri, Jan 11, 2002 at 11:54:24AM +0100, Maciej W. Rozycki wrote: > On Thu, 10 Jan 2002, Jun Sun wrote: > > > The current MIPS_ATOMIC set code for no-LLSC case does a load and store with > > interrupt open. This is potentially dangerous as an interrupt could happen > > in-between and cause the value changed inside the interrupt handler. > > No need to -- no sane interrupt handler will ever access a user's atomic > variable. > OK, I have to reveal the secret desire :-). I have a patch that makes MIPS kernel preemptible, and that unprotected operation becomes very volunerable with the preemptible patch. Jun
