Alice Hennessy wrote: > Ralf Baechle wrote: > > > On Mon, Oct 29, 2001 at 04:17:23PM -0800, Alice Hennessy wrote: > > > > > > This doesn't look right, you still need to enable the CU1 bit in the > > > > status register to let the FP emulator kick-in. FPU-less CPUs should > > > > take a coprocessor unusable exception on any floating-point instructions. > > > > I have been running this on several FPU-less CPUs, and it works fine for > > > me. > > > > > > Maybe the FPU-less CPUs you have been using define the CU1 bit as reserved > > > or is unused (ignore on write, zero on read)? The TX3927 actually allows > > > the setting of the CU1 bit. Have you seen a case where you need to set > > > the CU1 bit for the emulation to kick-in? I would think that the CU1 > > > bit should never be set to one for FPU-less CPUs. > > > > There are subtle differences in how CUx bits for unimplemented coprocessors > > are handled in the various processors. MIPS32 and MIPS64 specifies the > > behaviour as 0 on read, writes ignored; previous processors such as the > > R4000 handled this differently and as a consequence a fp instruction on > > a fpu-less r4000 class cpu may either throw a CU or a reserved instruction > > exception. To make things easier for everybody this is documented in the > > R10000 user's manual ... > > > > Ralf > > So, we should not set CU1 generically for FPU-less CPUs especially since a > known problem exists > for the tx3927? Ie, qualify all setting of CU1 as follows: > > if (mips_cpu.options & MIPS_CPU_FPU) > set_cp0_status(ST0_CU1); And while we are at it, could we handle the CP0 hazard of 4 nops, between setting the CU1 bit in the status register and executing the first floating point instruction, on CPU which got a FPU. > > > Alice -- _ _ ____ ___ Carsten Langgaard Mailto:carstenl@mips.com |\ /|||___)(___ MIPS Denmark Direct: +45 4486 5527 | \/ ||| ____) Lautrupvang 4B Switch: +45 4486 5555 TECHNOLOGIES 2750 Ballerup Fax...: +45 4486 5556 Denmark http://www.mips.com
