On Tue, Aug 21, 2001 at 09:34:00AM +0800, machael thailer wrote: > I am confused about CU0 and UM(ERL EXL) bit of STATUS register. > > The user manual says that " CP0 is always usable when in Kernel mode, > regardless of the setting of CU0 bit". Does it mean that when in Kernel mode > , the CU0 bit is always 1 and in User mode, the CU0 bit is 0? If the CU0 is > 0, can we be sure that it is in User mode? In the Linux kernel CU0 is used to indicate that we're running on the kernel stack. > If a user program is running in User mode, an interrupt happens at this > time(or an error occurs), then it will switch to Kernel mode to run the > interrupt handler(or the error exception handler). We know that the EXL(or > ERL) bit of Status register will be set to 1 by hardware. What about the UM > bit of Status? Does it remain unchangeable or change to 1 too? The user > manual doesn't say anything about it. The hardware does not change UM (r4k: KSU bits). > Another question about exception priority: > In entry.S, some exception handlers enables global interrupt bit(IE) but > others disables it. We have to avoid infinite recursion of exceptions; in same cases it's just paranoia or minor performance issue. > Also syscall exception handler enables global interrupt bit(IE). Since the > interrupt priority is lowest,If an interrupt happens in a syscall exception > handler, will it pause the syscall exception handler and run the interrupt > handler? If not, why it enable the IE bit(STI) in the syscall exception > handler?? > > If two interrupts happens at the same time, how can we decide the larger > priority interrupt and run its ISR? That's the decission of implementor of the respective board. No strict rules here; in general we priorize the timer interrupt highest but that's no longer mandatory. Ralf
