Re: i2c multimaster and the device driver detect function

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On 2013-05-08, at 13:54, Guenter Roeck wrote:

> [...]
> Isn't it the point of having multiple masters on the same bus, that each of
> them can manage the same devices ?

I wouldn't think so. You mention why in your last paragraph and I totally see
and agree with that. So that is not my intention at all.

> 
> Question for me is why you would want two masters in the same system context
> point to the same I2C bus. Usually the second master would be something like an
> IPMI controller or a second CPU/controller board in a redundant system.

I guess that's one scenario. In our scenario, we have an assambled board stack.
The main board has a sub-par i2c master onto which heavy slaves such as the
ad7147 capacitive input device consumes too much cpu power (cpu has to poll the
Kontron PLD which houses the i2c master core). Our hoped solution was to
allocate an i2c IP core in our FPGA. But board inter-connect budget didn't allow
for separate i2c segments, especially in the light that both master are said to
support multimaster operation. I got this working experimentally right now, I
just stumbled on jc42's detect, and am trying to project this kind of design to
the future. Right now, my only solution is to patch my version of jc42 not to
auto-detect, and explicitely enumerate my temperature sensors like my other
slaves in arch setup... yikes.

> 
> Even then the multi-master scenario is problematic, as you still end up with
> multiple masters controlling the same device. That is a problem inherent to I2C,
> and especially problematic with multi-page devices (typical problem: master 1
> sets page, master 2 sets page, master 1 accesses wrong data). I don't think there
> is a clean solution to solve that, other than to block i2c access for one of the
> masters entirely.

Other than the redundant/resiliency scenario, why would you setup the same slave
on two different masters? Right now I have a working setup where some slaves are
declared on bus 0 (PLD i2c master) and others on bus 1 (FPGA i2c master). I have
yet to stress test the setup within the next day or so, but so far, it seems to
work ok.

Thoughts?
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