On Tue, 20 Jul 2010 17:20:14 +0800, Gong Chen wrote: > On Tue, Jul 20, 2010 at 3:10 PM, Jean Delvare <khali@xxxxxxxxxxxx> wrote: > > On Tue, 20 Jul 2010 10:53:49 +0800, Chen Gong wrote: > >> >> mechanism will perform actions to forcibly cool down the processor. Alarm > >> >> may be raised, if the temperature grows enough (more than TjMax) to trigger > >> >> the Out-Of-Spec bit. Following table summarizes the exported sysfs files: > >> >> @@ -38,3 +38,103 @@ temp1_label - Contains string "Core X", where X is processor > >> >> The TjMax temperature is set to 85 degrees C if undocumented model specific > >> >> register (UMSR) 0xee has bit 30 set. If not the TjMax is 100 degrees C as > >> >> (sometimes) documented in processor datasheet. > >> >> + > >> >> +Appendix A. Known TjMax lists (TBD): > >> >> +Some information comes from ark.intel.com > >> >> + > >> >> +Process Processor TjMax(C) > >> >> + > >> >> +32nm Core i3/i5/i7 Processors > >> >> + i7 660UM/640/620, 640LM/620, 620M, 610E 105 > >> >> + i5 540UM/520/430, 540M/520/450/430 105 > >> >> + i3 330E, 370M/350/330 90 rPGA, 105 BGA > >> >> + i3 330UM 105 > >> >> + > >> >> +32nm Core i7 Extreme Processors > >> >> + 980X 100 > >> >> + > >> >> +32nm Celeron Processors > >> >> + U3400 105 > >> >> + P4505/P4500 90 > >> >> + > >> >> +45nm Xeon Processors 5400 Quad-Core > >> >> + X5492, X5482, X5472, X5470, X5460, X5450 85 > >> >> + E5472, E5462, E5450/40/30/20/10/05 85 > >> >> + L5408 95 > >> >> + L5430, L5420, L5410 70 > >> >> + > >> >> +45nm Xeon Processors 5200 Dual-Core > >> >> + X5282, X5272, X5270, X5260 90 > >> >> + E5240, E5220, E5205 90 > >> >> + E5205, E5220 70 > > > > The E5220 and E5205 are listed twice. > > > This is it from original doc > (http://edc.intel.com/Download.aspx?id=2612&returnurl=/default.aspx) > I think it is because different seal or usage. Maybe I can change it > to another style, such as "70, 90" > to cover this kind of situation. Yes, I think it would be better to list each model only once, with multiple temperature values if needed. Otherwise the reader is likely to miss it. -- Jean Delvare _______________________________________________ lm-sensors mailing list lm-sensors@xxxxxxxxxxxxxx http://lists.lm-sensors.org/mailman/listinfo/lm-sensors
