On 10/25/2010 03:16 AM, Ricardo MartÃnez wrote: > Dear all, > > I would like to know how a x86 CPU would behave in the following scenarios: > > 1) CPU is fetching data from memory, p.e. > movl eax, [esi] > > Imagine that instruction causes a cache miss. Then CPU has to access main > memory in order to get that data, which it takes a few clock cycles. > While CPU is accessing bus & chipset to get data from RAM memory, a > non-mapped IRQ is raised in interrupt controller. > What happens next? Is memory fetching discarded in order to serve interrupt > service routine as soon as posible? Or, on the other way, does CPU waits > until bus access completion before serving interrupt request? > Other assumptions would be worst case posible, I mean, single core CPU, > single memory controller/single bus, no HyperThreading (no parallel CPU > threads) and calling Interrupt Service Routine causes another cache miss and > another access to system bus. > In other words, are memory read/write instructions like the one above > atomic? > It depends on the cache attributed on the memory in question. For the strictest memory types, like uncached (UC), the entire CPU core stops until the bus transaction is complete. On the other hand, for cacheable memory types like writeback (WB) memory type usually associated with conventional RAM, the core would be interrupted but the data would still be loaded into the cache when it arrives (so when the instruction is re-executed it doesn't need to go out to memory.) > 2) In an embedded system I'm designing, I have a PCIe peripheral which is > accessed as memory mapped I/O. This peripheral can also generate interrupts. > I wonder what it is going to happen if I'm reading the contents of a 32 bit > register of this peripheral while it raises an IRQ. I do not want to disable > interrupts either masking this IRQ line > If chipset and PCIe bus are in use because of a read/write request from > non-irq context, and in the meantime the same PCIe peripheral raises an > interrupt, will CPU wait until completion of the read/write request > before serving Interrupt service routine, which will include another > read/write request for, p.e., Status Register of the peripheral? Assuming your PCIe BAR that contains your register is non-prefetchable and it is marked Uncacheable in your driver, you should be fine. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. -- To unsubscribe from this list: send the line "unsubscribe linux-x86_64" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
