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[PATCH] ath9k_hw: disable PLL / Clkreq for ASPM for AR9003

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This changes the PCIE PHY programming for better interoperability
with ASPM states. Without this AR9003 chipsets will hang when
using ASPM. This reproducible against an Apple Airport Extreme AP
by simply pinging it.

Cc: stable@xxxxxxxxxx
Cc: Jack Lee <jack.lee@xxxxxxxxxxx>
Cc: Carl Huang <carl.huang@xxxxxxxxxxx>
Cc: David Quan <david.quan@xxxxxxxxxxx>
Cc: Nael Atallah <nael.atallah@xxxxxxxxxxx>
Cc: Sarvesh Shrivastava <sarvesh.shrivastava@xxxxxxxxxxx>
Signed-off-by: Luis R. Rodriguez <lrodriguez@xxxxxxxxxxx>
---
 drivers/net/wireless/ath/ath9k/ar9003_hw.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
index 6137634..06fb2c8 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
@@ -146,8 +146,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
 		/* Sleep Setting */
 
 		INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
-				ar9300PciePhy_clkreq_enable_L1_2p2,
-				ARRAY_SIZE(ar9300PciePhy_clkreq_enable_L1_2p2),
+				ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
+				ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 				2);
 
 		/* Fast clock modal settings */
-- 
1.7.3.2.90.gd4c43

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