On Wed, Dec 01, 2010 at 10:09:24PM +0530, Felix Fietkau wrote:
> On 2010-12-01 8:32 AM, Vasanthakumar Thiagarajan wrote:
> > Signed-off-by: Vasanthakumar Thiagarajan <vasanth@xxxxxxxxxxx>
> > ---
> > drivers/net/wireless/ath/ath9k/ar9003_phy.c | 16 ++++++++++------
> > drivers/net/wireless/ath/ath9k/hw.c | 7 ++++++-
> > drivers/net/wireless/ath/ath9k/reg.h | 2 ++
> > 3 files changed, 18 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> > index b34a9e9..4e35bda 100644
> > --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> > +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
> > @@ -390,14 +390,18 @@ static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
> > {
> > u32 pll;
> >
> > - pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
> > + if (AR_SREV_9485(ah))
> > + pll = 0x142c;
> > + else {
> > + pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
> >
> > - if (chan && IS_CHAN_HALF_RATE(chan))
> > - pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
> > - else if (chan && IS_CHAN_QUARTER_RATE(chan))
> > - pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
> > + if (chan && IS_CHAN_HALF_RATE(chan))
> > + pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
> > + else if (chan && IS_CHAN_QUARTER_RATE(chan))
> > + pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
> >
> > - pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
> > + pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
> > + }
> >
> > return pll;
> > }
> NACK for this part. Take a look at what gets set for the older chips:
>
> 0x5 << AR_RTC_9300_PLL_REFDIV_S == 0x1400
> 0x2c << AR_RTC_9300_PLL_DIV_S == 0x002c
True, but older ar9003 chips have half/quarter rate support (which is not
implemented right now), in that case pll configuration would differ
for AR9485.
Vasanth
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