Josh,
> > > These kind of problems could be caused by using a wrong reference clock
> > > value. Could you please double check that the reference clock
> > > (board_ref_clock) matches the reference clock connected to the wl1271?
> > >
> > > Regards,
> > > Ido.
> >
> > Does board_ref_clock refer to the SLOW_CLK signal fed to the TiWi board?
>
> Oops, I see now I was confused on this point. It appears board_ref_clock
> refers to the SDIO clock line, correct? It appears that my MMC/SDIO
> interface is auto-configuring itself to 25MHz. Is this close enough to
> 26MHz, or do you think I should look into adjusting/forcing the
> interface to operate at one of the rates listed in wl12xx/boot.c?
>
25MHz for the SDIO clock is a correct value.
However, I believe the issue discussed is more related to the fast clock (reference clock) supplied to the WL1271 chip itself and not to the SDIO bus.
This is most probably a 26MHz clock but you'd better verify how your hardware is wired.
Regards,
Oz.
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