2010/9/22 Christian Lamparter <chunkeey@xxxxxxxxxxxxxx>:
> their GPL driver looks funny. (Max, it's really worth a look)
> anyway found this:
> /*
> Sequence taken from STLC4560 DataSheet
> This sequence can be run with the maximum SPI clock frequency (that is, 48 MHz).
> 1. Power up.
> 2. Wait 240 ms.
> 3. Halt processor (EHostDeviceCntrl2 = KSetHostOverride | KSetHostCPUEn=0).
> 4. Wait 1 us.
> 5. Enable DMA TX (EHostDmaTxCntrl, KDmaTxCntrlEnable).
> 6. Write DMA TX length (EHostDmaTxLength).
> 7. Write DMA TX base (EHostDmaTxBase1).
> 8. Wait 1 ìs.
> 9. Write firmware image (EHostDmaData).
> 10. RAM reset (EHostDeviceCntrl2 = KSetHostOverride | KSetHostReset | KSetRamBoot).
> 11. Wait 40 ms.
> 12. RAM boot (EHostDeviceCntrl2 = KSetHostOverride | KSetRamBoot),
> 13. Enable host interrupts (EHostIntEnable1 = KIrqReady | KIrqWrReady | KHwUpdate | KSwUpdate).
> 14. Wait for the READY interrupt (100 ms timeout).
> 15. Acknowledge the READY interrupt.
> 16. Issue the SLEEP interrupt.
> */
>
> maybe it helps
Yes. I see this code. But in p54spi.c I found sequence from 1 to 13.
Sagrad make this steps with disabler interrupt from card (poll chip
register). But p54spi wait hardware READY IRQ from chip in 14 (and in
IRQ routine send acknowledge from 15).
I think about rewrite this driver complete, but... This solution not so pretty.
// stage 13
/* enable host interrupts */
p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
cpu_to_le32(SPI_HOST_INTS_DEFAULT));
// stage 10
/* boot the device */
p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
SPI_CTRL_STAT_RAM_BOOT));
msleep(TARGET_BOOT_SLEEP);
//stage 12
p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
msleep(TARGET_BOOT_SLEEP);
May be after RAM BOOT interrupts in chip disabled?
--
Sincerely,
Alex A. Mihaylov
AKA MinimumLaw
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