On Tue June 22 2010 04:28:02 Jaroslav Fojtik wrote:
> root@dvouramenna:~# dmesg |grep "ath5.*chip"
> [ 6.632843] ath5k phy0: Atheros AR2413 chip found (MAC: 0x78, PHY: 0x45)
> [ 7.101528] ath5k phy1: Atheros AR5213A chip found (MAC: 0x59, PHY:
> 0x43)
>
> Both chipsets suffer with a same problem.
hi jara!
thanks, i was able to reproduce the problem here. can you try this patch, it
should fix it. it's just one line, so you could also change that 1 to a 4 in
the code directly. please let me know if it helps...
bruno
commit 36c597b80813988f6a9c47ca4a5cb5306bbc67fa
Author: Bruno Randolf <br1@xxxxxxxxxxx>
Date: Tue Jun 22 12:37:34 2010 +0900
ath5k: fix antenna div gc for <= AR5K_SREV_PHY_2413
Commit 39d5b2c83ca8904b6826a0713263a4e5a9c0730a "ath5k: update
AR5K_PHY_RESTART_DIV_GC values to match masks" introduced a regression on
PHY
chips older than AR5K_SREV_PHY_5413, which caused signal values to be
about
10dB less that before. This patch reverts the AR5K_PHY_RESTART_DIV_GC
values to
the same values which were effectively used before (without the bitmask
mistake). This brings signal levels back to normal on these PHY chips.
Signed-off-by: Bruno Randolf <br1@xxxxxxxxxxx>
diff --git a/drivers/net/wireless/ath/ath5k/phy.c
b/drivers/net/wireless/ath/ath5k/phy.c
index 82720fc..2254cd1 100644
--- a/drivers/net/wireless/ath/ath5k/phy.c
+++ b/drivers/net/wireless/ath/ath5k/phy.c
@@ -1768,7 +1768,7 @@ ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode,
bool enable)
if (enable) {
AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
- AR5K_PHY_RESTART_DIV_GC, 1);
+ AR5K_PHY_RESTART_DIV_GC, 4);
AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
AR5K_PHY_FAST_ANT_DIV_EN);
--
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