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Re: [ath9k-devel] [PATCH] ath5k: fix requested allocated RX skb size for DMA

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On Wed, Aug 12, 2009 at 2:48 PM, Luis R.
Rodriguez<lrodriguez@xxxxxxxxxxx> wrote:
> On Wed, Aug 12, 2009 at 11:13 AM, Jiri Slaby<jirislaby@xxxxxxxxx> wrote:
>> What was the exact purpose of this? My guess is that we should map
>> starting at a next cache line boundary and put this aligned address to
>> the device instead?
>
> I've heard two theories:
>
> 1) AR5210 *required* it otherwise bad we would get bad data
> 2) Performance considerations

>From what I can tell Jiri has the right guess:

  // ?? nice pointer arithmetic... should use PTR_ALIGN here?
  off = ((unsigned long) skb->data) % sc->cachelsz;
  if (off != 0)
      skb_reserve(skb, sc->cachelsz);

in other words, when we allocate, round up to the next cache line
greater than IEEE80211_MAX_LEN, then add an extra cache_line-1
bytes so we can map starting from it.

dev_alloc_skb already does some padding and alignment, and it's
configurable on a per-arch basis (though looks like only powerpc
sets it to L1 cache size, everywhere else it's 32 bytes.)

I guess if someone is bored some benchmarking would be useful.

-- 
Bob Copeland %% www.bobcopeland.com
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