On Wed, 2024-03-20 at 21:38 +0200, Bitterblue Smith wrote:
>
> These contain mostly the calibration and channel switching routines
> for RTL8192DU.
>
> Signed-off-by: Bitterblue Smith <rtl8821cerfe2@xxxxxxxxx>
>
Please fix these ones:
CHECK: Blank lines aren't necessary before a close brace '}'
#1157: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c:1139:
+
+ }
CHECK: Blank lines aren't necessary before a close brace '}'
#1303: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c:1285:
+
+ }
CHECK: Blank lines aren't necessary before a close brace '}'
#2702: FILE: drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c:2684:
+
+ }
> ---
> .../wireless/realtek/rtlwifi/rtl8192du/phy.c | 3051 +++++++++++++++++
> .../wireless/realtek/rtlwifi/rtl8192du/phy.h | 32 +
> 2 files changed, 3083 insertions(+)
> create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c
> create mode 100644 drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h
>
> diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c
> b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c
> new file mode 100644
> index 000000000000..7620fc6ab281
> --- /dev/null
> +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.c
> @@ -0,0 +1,3051 @@
[...]
> +
> +static u32 rf_reg_for_5g_swchnl_normal[MAX_RF_IMR_INDEX_NORMAL] = {
static const for this and every table below.
> + 0, 0x2f, 0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x0
> +};
> +
> +static u8 rf_reg_for_c_cut_5g[RF_REG_NUM_FOR_C_CUT_5G] = {
> + RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G4, RF_SYN_G5, RF_SYN_G6
> +};
> +
> +static u8 rf_reg_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
> + RF_SYN_G1, RF_SYN_G2, RF_SYN_G3, RF_SYN_G7, RF_SYN_G8
> +};
> +
> +static u8 rf_for_c_cut_5g_internal_pa[RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
> + 0x0B, 0x48, 0x49, 0x4B, 0x03, 0x04, 0x0E
> +};
> +
> +static u32 rf_reg_mask_for_c_cut_2g[RF_REG_NUM_FOR_C_CUT_2G] = {
> + BIT(19) | BIT(18) | BIT(17) | BIT(14) | BIT(1),
> + BIT(10) | BIT(9),
> + BIT(18) | BIT(17) | BIT(16) | BIT(1),
> + BIT(2) | BIT(1),
> + BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11)
> +};
> +
> +static u8 rf_chnl_5g[RF_CHNL_NUM_5G] = {
> + 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108,
> + 112, 116, 120, 124, 128, 132, 136, 140
> +};
> +
> +static u8 rf_chnl_5g_40m[RF_CHNL_NUM_5G_40M] = {
> + 38, 42, 46, 50, 54, 58, 62, 102, 106, 110, 114,
> + 118, 122, 126, 130, 134, 138
> +};
> +
> +static u32 rf_reg_pram_c_5g[5][RF_REG_NUM_FOR_C_CUT_5G] = {
> + {0xE43BE, 0xFC638, 0x77C0A, 0xDE471, 0xd7110, 0x8EB04},
> + {0xE43BE, 0xFC078, 0xF7C1A, 0xE0C71, 0xD7550, 0xAEB04},
> + {0xE43BF, 0xFF038, 0xF7C0A, 0xDE471, 0xE5550, 0xAEB04},
> + {0xE43BF, 0xFF079, 0xF7C1A, 0xDE471, 0xE5550, 0xAEB04},
> + {0xE43BF, 0xFF038, 0xF7C1A, 0xDE471, 0xd7550, 0xAEB04}
> +};
> +
> +static u32 rf_reg_param_for_c_cut_2g[3][RF_REG_NUM_FOR_C_CUT_2G] = {
> + {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},
> + {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},
> + {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}
> +};
> +
> +static u32 rf_syn_g4_for_c_cut_2g = 0xD1C31 & 0x7FF;
> +
> +static u32 rf_pram_c_5g_int_pa[3][RF_REG_NUM_FOR_C_CUT_5G_INTERNALPA] = {
> + {0x01a00, 0x40443, 0x00eb5, 0x89bec, 0x94a12, 0x94a12, 0x94a12},
> + {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a52, 0x94a52, 0x94a52},
> + {0x01800, 0xc0443, 0x00730, 0x896ee, 0x94a12, 0x94a12, 0x94a12}
> +};
> +
[...]
> +/* To avoid miswrite Reg0x800 for 92D */
> +static void rtl92d_phy_set_bb_reg_1byte(struct ieee80211_hw *hw,
> + u32 regaddr, u32 bitmask, u32 data)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + u32 originalvalue, bitshift, offset = 0;
> + u8 value = 0;
No need initializor of offset and value.
> +
> + /* BitMask only support bit0~bit7 or bit8~bit15, bit16~bit23,
> + * bit24~bit31, should be in 1 byte scale;
> + */
> + bitshift = calculate_bit_shift(bitmask);
> + offset = bitshift / 8;
> +
> + originalvalue = rtl_read_dword(rtlpriv, regaddr);
> + data = (originalvalue & (~bitmask)) | ((data << bitshift) & bitmask);
> +
> + value = (u8)(data >> (8 * offset));
No need casting of u8
> +
> + rtl_write_byte(rtlpriv, regaddr + offset, value);
> +}
> +
[...]
> +static void rtl92d_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band)
> +{
>
[...]
> + if (rtlhal->current_bandtype == BAND_ON_2_4G) {
> + value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
> + 0 ? REG_MAC0 : REG_MAC1));
> + value8 |= BIT(1);
> + rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
> + 0 ? REG_MAC0 : REG_MAC1), value8);
This will be clearer:
u32 reg = rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1;
if (rtlhal->current_bandtype == BAND_ON_2_4G) {
value8 = rtl_read_byte(rtlpriv, reg);
value8 |= BIT(1);
rtl_write_byte(rtlpriv, reg, value8);
} else {
value8 = rtl_read_byte(rtlpriv, reg);
value8 &= (~BIT(1));
rtl_write_byte(rtlpriv, reg, value8);
}
> + } else {
> + value8 = rtl_read_byte(rtlpriv, (rtlhal->interfaceindex ==
> + 0 ? REG_MAC0 : REG_MAC1));
> + value8 &= (~BIT(1));
no need parenthesis
> + rtl_write_byte(rtlpriv, (rtlhal->interfaceindex ==
> + 0 ? REG_MAC0 : REG_MAC1), value8);
> + }
> + mdelay(1);
> + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "<==Switch Band OK\n");
> +}
> +
>
[...]
> +static void _rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw, long result[][8],
> + u8 t, bool is2t)
> +{
> + static u32 adda_reg[IQK_ADDA_REG_NUM] = {
> + RFPGA0_XCD_SWITCHCONTROL, RBLUE_TOOTH, RRX_WAIT_CCA,
> + RTX_CCK_RFON, RTX_CCK_BBON, RTX_OFDM_RFON, RTX_OFDM_BBON,
> + RTX_TO_RX, RTX_TO_TX, RRX_CCK, RRX_OFDM, RRX_WAIT_RIFS,
> + RRX_TO_RX, RSTANDBY, RSLEEP, RPMPD_ANAEN
> + };
> + static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
> + REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG
> + };
> + static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
> + RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
> + RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
> + RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
> + RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
> + ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
> + };
static const
[...]
> +static void _rtl92d_phy_iq_calibrate_5g_normal(struct ieee80211_hw *hw,
> + long result[][8], u8 t)
> +{
> + static u32 adda_reg[IQK_ADDA_REG_NUM] = {
> + RFPGA0_XCD_SWITCHCONTROL, RBLUE_TOOTH, RRX_WAIT_CCA,
> + RTX_CCK_RFON, RTX_CCK_BBON, RTX_OFDM_RFON, RTX_OFDM_BBON,
> + RTX_TO_RX, RTX_TO_TX, RRX_CCK, RRX_OFDM, RRX_WAIT_RIFS,
> + RRX_TO_RX, RSTANDBY, RSLEEP, RPMPD_ANAEN
> + };
> + static u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
> + REG_TXPAUSE, REG_BCN_CTRL, REG_BCN_CTRL_1, REG_GPIO_MUXCFG
> + };
> + static u32 iqk_bb_reg[IQK_BB_REG_NUM] = {
> + RFPGA0_XAB_RFINTERFACESW, RFPGA0_XA_RFINTERFACEOE,
> + RFPGA0_XB_RFINTERFACEOE, ROFDM0_TRMUXPAR,
> + RFPGA0_XCD_RFINTERFACESW, ROFDM0_TRXPATHENABLE,
> + RFPGA0_RFMOD, RFPGA0_ANALOGPARAMETER4,
> + ROFDM0_XAAGCCORE1, ROFDM0_XBAGCCORE1
> + };
static const
[...]
> +static void _rtl92d_phy_reload_lck_setting(struct ieee80211_hw *hw, u8 channel)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + u8 erfpath = rtlpriv->rtlhal.current_bandtype ==
> + BAND_ON_5G ? RF90_PATH_A :
> + IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ?
> + RF90_PATH_B : RF90_PATH_A;
u8 erfpath = rtlpriv->rtlhal.current_bandtype == BAND_ON_5G ? RF90_PATH_A :
IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ? RF90_PATH_B : RF90_PATH_A;
or
u8 erfpath =
rtlpriv->rtlhal.current_bandtype == BAND_ON_5G ? RF90_PATH_A :
IS_92D_SINGLEPHY(rtlpriv->rtlhal.version) ? RF90_PATH_B : RF90_PATH_A;
> + bool bneed_powerdown_radio = false;
> + u32 u4tmp = 0, u4regvalue = 0;
no need initializors
[...]
> +static void _rtl92d_phy_lc_calibrate_sw(struct ieee80211_hw *hw, bool is2t)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
> + u32 curvecount_val[CV_CURVE_CNT * 2] = {0};
do memset() on this below, no need to initialize it here.
Also, if you need, just '= {}'.
> + u16 timeout = 800, timecount = 0;
> + u32 u4tmp, offset, rf_syn_g4[2];
> + u8 tmpreg, index, rf_mode[2];
> + u8 path = is2t ? 2 : 1;
> + u8 i;
> +
> + /* Check continuous TX and Packet TX */
> + tmpreg = rtl_read_byte(rtlpriv, 0xd03);
> + /* if Deal with contisuous TX case, disable all continuous TX */
> + /* if Deal with Packet TX case, block all queues */
> + if ((tmpreg & 0x70) != 0)
> + rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
> + else
> + rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
adding proper blank line will make code more readable.
> + rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0xF00000, 0x0F);
> + for (index = 0; index < path; index++) {
> + /* 1. Read original RF mode */
> + offset = index == 0 ? ROFDM0_XAAGCCORE1 : ROFDM0_XBAGCCORE1;
> + rf_mode[index] = rtl_read_byte(rtlpriv, offset);
> + /* 2. Set RF mode = standby mode */
> + rtl_set_rfreg(hw, (enum radio_path)index, RF_AC,
> + RFREG_OFFSET_MASK, 0x010000);
> +
> + rf_syn_g4[index] = rtl_get_rfreg(hw, index, RF_SYN_G4,
> + RFREG_OFFSET_MASK);
> + rtl_set_rfreg(hw, index, RF_SYN_G4, 0x700, 0x7);
> +
> + /* switch CV-curve control by LC-calibration */
> + rtl_set_rfreg(hw, (enum radio_path)index, RF_SYN_G7,
> + BIT(17), 0x0);
> + /* 4. Set LC calibration begin */
> + rtl_set_rfreg(hw, (enum radio_path)index, RF_CHNLBW,
> + 0x08000, 0x01);
> + }
> +
[...]
> +void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_hal *rtlhal = &rtlpriv->rtlhal;
> + struct rtl_phy *rtlphy = &rtlpriv->phy;
> + u32 timeout = 2000, timecount = 0;
> +
> + while (rtlpriv->mac80211.act_scanning && timecount < timeout) {
> + udelay(50);
> + timecount += 50;
What is the purpose?
Even if you really need it, just mdelay(2) or something like that?
> + }
> +
> + rtlphy->lck_inprogress = true;
> + RTPRINT(rtlpriv, FINIT, INIT_IQK,
> + "LCK:Start!!! currentband %x delay %d ms\n",
> + rtlhal->current_bandtype, timecount);
> +
> + _rtl92d_phy_lc_calibrate_sw(hw, is2t);
> +
> + rtlphy->lck_inprogress = false;
> + RTPRINT(rtlpriv, FINIT, INIT_IQK, "LCK:Finish!!!\n");
> +}
> +
[...]
> +u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw)
> +{
> +
[...]
> + while (rtlphy->lck_inprogress && timecount < timeout) {
> + mdelay(50);
> + timecount += 50;
> + }
Could LCK and switch channel happen simultaneously?
Can you point out the case?
> + if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY &&
> + rtlhal->bandset == BAND_ON_BOTH) {
> + ret_value = rtl_get_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
> + MASKDWORD);
> + if (rtlphy->current_channel > 14 && !(ret_value & BIT(0)))
> + rtl92d_phy_switch_wirelessband(hw, BAND_ON_5G);
> + else if (rtlphy->current_channel <= 14 && (ret_value & BIT(0)))
> + rtl92d_phy_switch_wirelessband(hw, BAND_ON_2_4G);
> + }
> + switch (rtlhal->current_bandtype) {
> + case BAND_ON_5G:
> + /* Get first channel error when change between
> + * 5G and 2.4G band.
> + */
> + if (WARN_ONCE(channel <= 14, "rtl8192de: 5G but channel<=14\n"))
> + return 0;
> + break;
> + case BAND_ON_2_4G:
> + /* Get first channel error when change between
> + * 5G and 2.4G band.
> + */
> + if (WARN_ONCE(channel > 14, "rtl8192de: 2G but channel>14\n"))
> + return 0;
> + break;
> + default:
> + WARN_ONCE(true, "rtl8192de: Invalid WirelessMode(%#x)!!\n",
> + rtlpriv->mac80211.mode);
> + break;
> + }
> + rtlphy->sw_chnl_inprogress = true;
> + if (channel == 0)
> + channel = 1;
Can this really happen?
[...]
> +static void _rtl92d_phy_set_rfon(struct ieee80211_hw *hw)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> +
> + /* a. SYS_CLKR 0x08[11] = 1 restore MAC clock */
> + /* b. SPS_CTRL 0x11[7:0] = 0x2b */
> + if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
> + rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
Please add proper blank lines.
> + /* c. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function */
> + rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
> + /* RF_ON_EXCEP(d~g): */
> + /* d. APSD_CTRL 0x600[7:0] = 0x00 */
> + rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
> + /* e. SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function again */
> + /* f. SYS_FUNC_EN 0x02[7:0] = 0xE3 enable BB TRX function*/
> + rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
> + rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
> + /* g. txpause 0x522[7:0] = 0x00 enable mac tx queue */
> + rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
> +}
> +
> +static void _rtl92d_phy_set_rfsleep(struct ieee80211_hw *hw)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + u32 u4btmp;
> + u8 delay = 5;
'retry' ?
> +
> + /* a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
> + rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
> + /* b. RF path 0 offset 0x00 = 0x00 disable RF */
> + rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
> + /* c. APSD_CTRL 0x600[7:0] = 0x40 */
> + rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
> + /* d. APSD_CTRL 0x600[7:0] = 0x00
> + * APSD_CTRL 0x600[7:0] = 0x00
> + * RF path 0 offset 0x00 = 0x00
> + * APSD_CTRL 0x600[7:0] = 0x40
> + */
> + u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
Proper blank lines:
> + while (u4btmp != 0 && delay > 0) {
> + rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
> + rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
> + rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
> + u4btmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
> + delay--;
> + }
> + if (delay == 0) {
> + /* Jump out the LPS turn off sequence to RF_ON_EXCEP */
> + rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
> +
> + rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
> + rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
> + rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
> + rtl_dbg(rtlpriv, COMP_POWER, DBG_LOUD,
> + "Fail !!! Switch RF timeout\n");
> + return;
> + }
> + /* e. For PCIE: SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB TRX function */
> + rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
> + /* f. SPS_CTRL 0x11[7:0] = 0x22 */
> + if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY)
> + rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
> + /* g. SYS_CLKR 0x08[11] = 0 gated MAC clock */
> +}
> +
> +bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
> + enum rf_pwrstate rfpwr_state)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
> + struct rtl_mac *mac = rtl_mac(rtlpriv);
> + bool bresult = true;
> +
> + if (rfpwr_state == ppsc->rfpwr_state)
> + return false;
> + switch (rfpwr_state) {
> + case ERFON:
> + if (ppsc->rfpwr_state == ERFOFF &&
> + RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
> + u32 initializecount = 0;
> + bool rtstatus;
> +
> + do {
> + initializecount++;
> + rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
> + "IPS Set eRf nic enable\n");
> + rtstatus = rtl_ps_enable_nic(hw);
> + } while (!rtstatus && (initializecount < 10));
> +
> + RT_CLEAR_PS_LEVEL(ppsc,
> + RT_RF_OFF_LEVL_HALT_NIC);
> + } else {
> + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
> + "awake, slept:%d ms state_inap:%x\n",
> + jiffies_to_msecs(jiffies -
> + ppsc->last_sleep_jiffies),
> + rtlpriv->psc.state_inap);
> + ppsc->last_awake_jiffies = jiffies;
> + _rtl92d_phy_set_rfon(hw);
> + }
> +
> + if (mac->link_state == MAC80211_LINKED)
> + rtlpriv->cfg->ops->led_control(hw,
> + LED_CTL_LINK);
> + else
> + rtlpriv->cfg->ops->led_control(hw,
> + LED_CTL_NO_LINK);
if (mac->link_state == MAC80211_LINKED)
rtlpriv->cfg->ops->led_control(hw, LED_CTL_LINK);
else
rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
> + break;
> + case ERFOFF:
> + if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
> + rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
> + "IPS Set eRf nic disable\n");
> + rtl_ps_disable_nic(hw);
> + RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
> + } else {
> + if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
> + rtlpriv->cfg->ops->led_control(hw,
> + LED_CTL_NO_LINK);
> + else
> + rtlpriv->cfg->ops->led_control(hw,
> + LED_CTL_POWER_OFF);
if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
rtlpriv->cfg->ops->led_control(hw, LED_CTL_NO_LINK);
else
rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
> + }
> + break;
> + case ERFSLEEP:
> + if (ppsc->rfpwr_state == ERFOFF)
> + return false;
> +
> + rtl_dbg(rtlpriv, COMP_POWER, DBG_DMESG,
> + "sleep awakened:%d ms state_inap:%x\n",
> + jiffies_to_msecs(jiffies -
> + ppsc->last_awake_jiffies),
> + rtlpriv->psc.state_inap);
> + ppsc->last_sleep_jiffies = jiffies;
> + _rtl92d_phy_set_rfsleep(hw);
> + break;
> + default:
> + pr_err("switch case %#x not processed\n",
> + rfpwr_state);
> + bresult = false;
return false directly?
> + break;
> + }
> + if (bresult)
> + ppsc->rfpwr_state = rfpwr_state;
> + return bresult;
> +}
> +
> +void rtl92d_phy_set_poweron(struct ieee80211_hw *hw)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
> + u8 value8;
> + u16 i;
> + u32 mac_reg = (rtlhal->interfaceindex == 0 ? REG_MAC0 : REG_MAC1);
reverse X'mas tree.
> +
> + /* notice fw know band status 0x81[1]/0x53[1] = 0: 5G, 1: 2G */
> + if (rtlhal->current_bandtype == BAND_ON_2_4G) {
> + value8 = rtl_read_byte(rtlpriv, mac_reg);
> + value8 |= BIT(1);
> + rtl_write_byte(rtlpriv, mac_reg, value8);
> + } else {
> + value8 = rtl_read_byte(rtlpriv, mac_reg);
> + value8 &= (~BIT(1));
> + rtl_write_byte(rtlpriv, mac_reg, value8);
> + }
> +
> + if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
> + value8 = rtl_read_byte(rtlpriv, REG_MAC0);
> + rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
> + } else {
> + mutex_lock(&globalmutex_power);
What do you need 'global' mutex? Usually, we want to support multiple instances
run simultaneously. Does this mutext across instances?
I feel not. Please move them into struct rtl_priv.
> + if (rtlhal->interfaceindex == 0) {
> + value8 = rtl_read_byte(rtlpriv, REG_MAC0);
> + rtl_write_byte(rtlpriv, REG_MAC0, value8 | MAC0_ON);
> + } else {
> + value8 = rtl_read_byte(rtlpriv, REG_MAC1);
> + rtl_write_byte(rtlpriv, REG_MAC1, value8 | MAC1_ON);
> + }
> + value8 = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
> + mutex_unlock(&globalmutex_power);
blank line. It would be clear to see lock/unlock.
> + for (i = 0; i < 200; i++) {
> + if ((value8 & BIT(7)) == 0)
> + break;
> +
> + udelay(500);
> + mutex_lock(&globalmutex_power);
> + value8 = rtl_read_byte(rtlpriv,
> + REG_POWER_OFF_IN_PROCESS);
> + mutex_unlock(&globalmutex_power);
> +
> + }
> + if (i == 200)
> + WARN_ONCE(true, "rtl8192de: Another mac power off over time\n");
> + }
> +}
> +
> +void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
> + struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
> + struct rtl_phy *rtlphy = &rtlpriv->phy;
> + u8 rfpath, i;
> +
> + rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "==>\n");
> + /* r_select_5G for path_A/B 0 for 2.4G, 1 for 5G */
> + if (rtlhal->current_bandtype == BAND_ON_2_4G) {
> + /* r_select_5G for path_A/B,0x878 */
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x0);
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x0);
> + if (rtlhal->macphymode != DUALMAC_DUALPHY) {
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x0);
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x0);
> + }
proper blank lines...
Please take a glance of whole patches, and add blank lines to make them readable.
> + /* rssi_table_select:index 0 for 2.4G.1~3 for 5G,0xc78 */
> + rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x0);
> + /* fc_area 0xd2c */
> + rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x0);
> + /* 5G LAN ON */
> + rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0xa);
> + /* TX BB gain shift*1,Just for testchip,0xc80,0xc88 */
> + rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
> + 0x40000100);
> + rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, MASKDWORD,
> + 0x40000100);
straighten these two lines.
> + if (rtlhal->macphymode == DUALMAC_DUALPHY) {
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
> + BIT(10) | BIT(6) | BIT(5),
> + ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
> + (rtlefuse->eeprom_c9 & BIT(1)) |
> + ((rtlefuse->eeprom_cc & BIT(1)) << 4));
> + rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
> + BIT(10) | BIT(6) | BIT(5),
> + ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
> + ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
> + ((rtlefuse->eeprom_cc & BIT(0)) << 5));
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0);
> +
> + rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038);
> + rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000);
> + } else {
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFINTERFACESW,
> + BIT(26) | BIT(22) | BIT(21) | BIT(10) |
> + BIT(6) | BIT(5),
> + ((rtlefuse->eeprom_c9 & BIT(3)) >> 3) |
> + (rtlefuse->eeprom_c9 & BIT(1)) |
> + ((rtlefuse->eeprom_cc & BIT(1)) << 4) |
> + ((rtlefuse->eeprom_c9 & BIT(7)) << 9) |
> + ((rtlefuse->eeprom_c9 & BIT(5)) << 12) |
> + ((rtlefuse->eeprom_cc & BIT(3)) << 18));
> + rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE,
> + BIT(10) | BIT(6) | BIT(5),
> + ((rtlefuse->eeprom_c9 & BIT(2)) >> 2) |
> + ((rtlefuse->eeprom_c9 & BIT(0)) << 1) |
> + ((rtlefuse->eeprom_cc & BIT(0)) << 5));
> + rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
> + BIT(10) | BIT(6) | BIT(5),
> + ((rtlefuse->eeprom_c9 & BIT(6)) >> 6) |
> + ((rtlefuse->eeprom_c9 & BIT(4)) >> 3) |
> + ((rtlefuse->eeprom_cc & BIT(2)) << 3));
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER,
> + BIT(31) | BIT(15), 0);
> +
> + rtl_set_bbreg(hw, RPDP_ANTA, MASKDWORD, 0x01017038);
> + rtl_set_bbreg(hw, RPDP_ANTB, MASKDWORD, 0x01017038);
> + rtl_set_bbreg(hw, RCONFIG_ANTA, MASKDWORD, 0x0f600000);
> + rtl_set_bbreg(hw, RCONFIG_ANTB, MASKDWORD, 0x0f600000);
> + }
> + /* 1.5V_LDO */
> + } else {
> + /* r_select_5G for path_A/B */
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(0), 0x1);
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(15), 0x1);
> + if (rtlhal->macphymode != DUALMAC_DUALPHY) {
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(16), 0x1);
> + rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(31), 0x1);
> + }
> + /* rssi_table_select:index 0 for 2.4G.1~3 for 5G */
> + rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, BIT(6) | BIT(7), 0x1);
> + /* fc_area */
> + rtl_set_bbreg(hw, ROFDM1_CFOTRACKING, BIT(14) | BIT(13), 0x1);
> + /* 5G LAN ON */
> + rtl_set_bbreg(hw, 0xB30, 0x00F00000, 0x0);
> +
> + /* TX BB gain shift,Just for testchip,0xc80,0xc88 */
> + if (rtlefuse->internal_pa_5g[rtlhal->interfaceindex])
> + rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
> + 0x2d4000b5);
> + else
> + rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, MASKDWORD,
> + 0x20000080);
> +
[...]
> +bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw)
> +{
> + struct rtl_priv *rtlpriv = rtl_priv(hw);
> + struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
> + u8 u1btmp;
> +
> + if (rtlhal->macphymode == SINGLEMAC_SINGLEPHY) {
> + u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
> + rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
No need parenthesis of (~MAC0_ON)
> + return true;
> + }
> + mutex_lock(&globalmutex_power);
Add blank lines to let lock/unlock more visible.
> + if (rtlhal->interfaceindex == 0) {
> + u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
> + rtl_write_byte(rtlpriv, REG_MAC0, u1btmp & (~MAC0_ON));
> + u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
> + u1btmp &= MAC1_ON;
> + } else {
> + u1btmp = rtl_read_byte(rtlpriv, REG_MAC1);
> + rtl_write_byte(rtlpriv, REG_MAC1, u1btmp & (~MAC1_ON));
> + u1btmp = rtl_read_byte(rtlpriv, REG_MAC0);
> + u1btmp &= MAC0_ON;
> + }
> + if (u1btmp) {
> + mutex_unlock(&globalmutex_power);
> + return false;
> + }
> + u1btmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
> + u1btmp |= BIT(7);
> + rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1btmp);
> + mutex_unlock(&globalmutex_power);
> + return true;
> +}
> +
[...]
> diff --git a/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h
> b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h
> new file mode 100644
> index 000000000000..df2b0b159fc2
> --- /dev/null
> +++ b/drivers/net/wireless/realtek/rtlwifi/rtl8192du/phy.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright(c) 2009-2012 Realtek Corporation.*/
> +
> +#ifndef __RTL92D_PHY_H__
> +#define __RTL92D_PHY_H__
__RTL92DU_PHY_H__ ?
