On 10/29/19 11:16 PM, zhichen@xxxxxxxxxxxxxx wrote:
On 2019-10-23 01:16, Peter Oh wrote:
How can you say value 0 (I believe it's 64 bytes) DMA burst size
causes the symptom and 1 fixes it?
Peter
Confirmed from HW team that the configuration controls AXI burst size
of the RD/WR access to the HOST MEM.
0- No split , RAW read/write transfer size from MAC is put out on
bus as burst length.
1- Split at 256 byte boundary
2,3- Reserved
I would ACK to this change. Although QCA4019 host mem max AXI read/write
registers have different descriptions from above, they say 1 (256-byte)
is default and the values, 0, 2, and 3 are reserved. So changing it back
to 1 is reasonable to me.
Thanks,
Peter
