On 2019-10-23 01:16, Peter Oh wrote:
How can you say value 0 (I believe it's 64 bytes) DMA burst size causes the symptom and 1 fixes it? Peter
Confirmed from HW team that the configuration controls AXI burst size of the RD/WR access to the HOST MEM. 0- No split , RAW read/write transfer size from MAC is put out on bus as burst length.
1- Split at 256 byte boundary 2,3- Reserved That's why we see issue with value 0. Zhi
